Platform Overview
Infrastructure at a Glance
Production-grade quantum computing infrastructure with fidelity-first routing and zero-queue execution.
913
Physical Qubits
Aggregate qubit capacity across all connected IBM Quantum Heron R3 backends
6
Heron R3 Backends
Fully connected IBM Quantum processors with heavy-hex topology
<10ms
Routing Latency
Fidelity-first algorithm routing to optimal backend in under 10 milliseconds
99.9%
Platform Uptime
Enterprise SLA with multi-backend failover and automatic circuit retry
0
Queue Wait
Zero-queue architecture eliminates shared-access contention
QEC
Error Correction
Surface code quantum error correction with real-time syndrome extraction
Backend Fleet
IBM Quantum Heron R3 Backends
Each backend features a heavy-hex connectivity topology optimized for error correction and high-fidelity gate operations.
| Backend |
Qubits |
Processor |
Topology |
2Q Gate Error |
T1 (median) |
| ibm_pittsburgh |
156 |
Heron R3 |
Heavy-hex |
2.1 x 10-3 |
287 μs |
| ibm_fez |
156 |
Heron R3 |
Heavy-hex |
1.9 x 10-3 |
312 μs |
| ibm_boston |
156 |
Heron R3 |
Heavy-hex |
2.3 x 10-3 |
274 μs |
| ibm_torino |
133 |
Heron R3 |
Heavy-hex |
2.0 x 10-3 |
298 μs |
| ibm_marrakesh |
156 |
Heron R3 |
Heavy-hex |
2.2 x 10-3 |
265 μs |
| ibm_kingston |
156 |
Heron R3 |
Heavy-hex |
2.1 x 10-3 |
291 μs |
Performance
Benchmark Results
Measured performance characteristics across production workloads.
Algorithm Routing Latency
< 10ms
Platform Uptime SLA
99.9%
Median 2Q Gate Error
2.1e-3
Median Readout Error
8.4e-3
Max Circuit Depth
5,000+
Concurrent Circuit Limit
300
QEC Logical Error Rate
10-6
Shot Throughput
100K/s
Algorithms
Supported Algorithm Families
Pre-optimized circuit templates with automatic transpilation and backend-specific calibration.
Grover's
Unstructured search
Supported Circuit Formats
OpenQASM 3.0
Qiskit QuantumCircuit
CUDA-Q Kernel
Cirq Circuit
PennyLane QNode
Error Correction
QEC Implementation Details
Surface code quantum error correction with real-time syndrome extraction and adaptive decoding.
Surface Code
Error Correction Code
Topological error correction with distance-3 and distance-5 codes. Stabilizer measurements performed via ancilla qubits with real-time classical feedback.
3 Decoders
Decoder Options
Steane code (fast, low overhead), NVIDIA QLDPC (GPU-accelerated, high distance), and Tensor Network (maximum fidelity, research workloads).
Real-Time
Syndrome Extraction
Sub-microsecond syndrome extraction with parity check circuits. Mid-circuit measurement and conditional reset for continuous error monitoring.
10-6
Logical Error Rate
Achieved logical error rate with distance-5 surface code. 1000x improvement over raw physical error rates through active error correction.
Compliance
Security & Compliance
Enterprise-grade security posture with continuous compliance monitoring and audit-ready documentation.
SOC2
SOC 2 Type II
Annual audit of security, availability, processing integrity, confidentiality, and privacy controls.
IL4
Impact Level 4
DoD information system authorization for Controlled Unclassified Information (CUI).
NIST
NIST 800-53
Federal information security controls framework with continuous monitoring and assessment.
GDPR
GDPR
EU General Data Protection Regulation compliance with data residency and right-to-erasure support.